The present invention relates to a phase-locked loop combining rapid lock acquisition with low power dissipation.
Phase-locked loops (PLLs) are widely used as frequency synthesizers in radio receivers and wireless telephone sets.
A conventional PLL comprises a reference oscillator, a voltage-controlled oscillator, a programmable frequency divider, a phase detector, and a low-pass filter. Various types of phase detectors are known, including phase detectors employing charge pumps.
A desirable capability in a PLL is the capability to lock onto new frequencies quickly. In certain types of wireless telephone sets, for example, the PLL needs to switch rapidly between the frequency of a traffic channel and the frequency of a control channel. Rapid frequency switching is also useful in radio receivers, for quick response to input from channel selection buttons.
In a conventional PLL, however, the lock acquisition time or lock-up time is determined by parameters such as the loop gain, the time constant of the low-pass filter, and the reference frequency, which is normally equal to or less than the channel spacing. When parameters that give optimum performance in the locked state are selected, the lock-up time tends to be undesirably long. In PLLs with charge-pump phase detectors, a particular problem is that the phase detector generates error signals only intermittently.
The lock-up time can be shortened by increasing the reference frequency to a value exceeding the channel spacing, but complex compensation circuitry then becomes necessary to receive channels with frequencies that are not integer multiples of the reference frequency.
Unexamined Japanese Patent Publication No. 69794/1994 discloses a PLL that accelerates the acquisition of phase lock by generating a reset signal when the desired frequency is reached, but this reset signal does not shorten the time required to reach the desired frequency.
The present inventor has proposed a PLL with multiple feedback loops, which shorten the entire lock-up process by increasing the loop gain, but these multiple feedback loops also increase the power dissipation of the PLL.
Much of the power dissipated in a PLL is dissipated by the programmable frequency divider, which has a complex internal structure and operates at the same high frequency as the voltage-controlled oscillator. Complementary metaloxide-semiconductor (CMOS) circuitry is commonly employed in the programmable frequency divider; power is dissipated by the rapid charging and discharging of a large number of capacitive loads in the CMOS circuits.
A known method of reducing power dissipation is to prescale the signals output from the reference oscillator and input to the programmable frequency divider, but this method causes a proportionate lengthening of the lock-up time.
In general, there is a trade-off between power dissipation and lock-up time in a PLL, one of these two characteristics being improved only at the expense of the other characteristic.